The present invention relates to ion implantation, and more particularly to ion implantation into a semiconductor substrate through a layer of electrically insulative material.
In ion implantation, it is, at the present time, a fairly prevalent practice to ion implant through a relatively thin passivating layer, such as silicon dioxide, having a thickness in the order of 100A to 1,000A instead of ion implanting directly into an exposed semiconductor substrate, such as silicon. This ion implantation through a relatively thin layer is utilized in combination with conventional ion implantation masking techniques. For example, the relatively thin layer may be masked with a material, such as photoresist, which masks the whole surface except for holes through the photoresist exposing the thin layer of insulative material in the regions which are to be ion implanted. Also, the relatively thin layers may be utilized in combination with relatively thick layers of the same material having sufficient thicknesses in the order of from 1,000A to 10,000A so that the ions being implanted do not have sufficient energy to pass through the thicker layers. In such a structure, the thicker portions of insulative material are placed over regions of the substrate which are to be free of the ion implantation.
The art has been moving in the direction of ion implantation through relatively thin layers of insulative material for several reasons. First, all of the semiconductor substrate remains covered during the introduction of the dopant, i.e., none of the substrate is exposed at any point to contaminants in the ambient. Secondly, at many processing stages in forming semiconductor devices, utilization of ion implantation through the passivating or insulative layer avoids the necessity of further masking and etching steps to remove particular portions of the passivating layer, e.g., ion implantation through the gate passivating layer in FET fabrication in order to tailor the conductivity of the channel under the gate. A third advantage is that where a high surface concentration or C.sub.0 of impurity in the semiconductor substrate is desired, ion implantation through an insulative layer functions as an aid in achieving a doping profile in the substrate which has a peak at the substrate surface.
In addition to these advantages recognized by the prior art, we have found that the layer of passivating material serves as a trap or catcher for ions of contaminating material within the ion beam. These contaminating ions in a large part result from collisions between the dopant ions of the beam and the ion implantation equipment, e.g., sidewalls or apertures of the defining equipment. We have further found that during the thermal drive-in step conventionally conducted at temperatures in the order of 1,000.degree.C to 1,200.degree.C, the contaminating ions which have been caught or trapped in the passivating layer tend to diffuse from the passivating layer into the substrate and, thereby, contaminate the ion implanted region in the substrate.
The standard contaminants which are caught or trapped in the passivating layer are ions of the material used in the ion implantation equipment. Among these contaminants are atoms or molecules from materials such as iron, nickel, chromium, manganese, or aluminum, as well as oil from vacuum pumps. In some cases, the contaminants result from materials used for masking purposes, e.g., some photoresist masks tend to produce carbon contaminants.